Field of the Invention
The present invention relates to a method of manufacturing a solid-state image sensor.
Description of the Related Art
A solid-state image sensor includes a plurality of pixels formed on a semiconductor substrate. Each pixel can include, for example, a charge accumulation region in which charges generated by photoelectric conversion are accumulated, a charge holding region (floating diffusion), a transistor which transfers the charges from the charge accumulation region to the charge holding region, and the like.
Some solid-state image sensor has a global electronic shutter function in order to equalize charge accumulation times among the pixels with each other. In such a solid-state image sensor, each pixel includes, for example, a charge accumulation region, the first charge holding region, the second charge holding region, the first transistor, and the second transistor. The first transistor is arranged between the charge accumulation region and the first charge holding region, and transfers charges from the charge accumulation region to the first charge holding region in accordance with a control signal. The second transistor is arranged between the first charge holding region and the second charge holding region, and transfers the charges from the first charge holding region to the second charge holding region in accordance with a control signal. The first transistors are controlled at once (controlled at substantially the same timing) in the plurality of pixels. This makes it possible to equalize the charge accumulation times among the pixels with each other. Then, the second transistor is controlled while selecting the plurality of pixels on the row basis, and signals each corresponding to an amount of the charges transferred to the second charge holding region of each pixel are read out sequentially as pixel signals.
That is, according to an example of the solid-state image sensor having the above-described global electronic shutter function, two charge transfer operations of the first charge transfer for equalizing the charge accumulation times among the pixels with each other and the second charge transfer for reading out the pixel signals based on thus obtained charges are performed sequentially.
As one of techniques of reducing noise components in the pixel signals, there is known a technique of making the charge accumulation region or the first charge holding region be a buried type. Paying attention to, for example, the charge accumulation region, it is possible to make the charge accumulation region be the buried type by forming, between the charge accumulation region and the upper surface of a semiconductor substrate, an impurity region of a conductivity type different from that of the charge accumulation region. This impurity region will be expressed as a “buried impurity region” hereinafter.
Note that in order to prevent a decrease in charge transfer efficiency by the first transistor, the buried impurity region is not preferably formed immediately below the gate electrode of the first transistor. More specifically, in a planar view (a planar view with respect to the upper surface of the semiconductor substrate; the same applies below), it is preferable that the buried impurity region and the gate electrode do not overlap each other (a gap exists between the buried impurity region and the gate electrode). This also applies to the second transistor.
International Publication No. 11/043432 (for example, FIGS. 6(d) to 6(f)) describes a method of forming a buried impurity region by forming a spacer (side spacer) on the side surface of a gate electrode, and then injecting an impurity using the gate electrode and the spacer as masks. According to this method, the buried impurity region is formed such that the buried impurity region and the gate electrode do not overlap each other in the planar view.
In general, a spacer is formed by forming a member for forming the spacer on a semiconductor substrate and a gate electrode and then etching it back, and silicon nitride or the like having a dielectric constant higher than that of a gate insulating film can be used for the spacer. Thus, forming the spacer can be a cause of increasing a parasitic capacitance applied to the gate electrode. Further, forming the spacer can generally be a cause of preventing scaling of a transistor size. For these reasons, a new technique of forming the buried impurity region without any spacer is required.